Method for generating a gamma voltage, driving circuit therefor, and display device

ABSTRACT

A method for generating a gamma voltage comprising, a first low voltage and a first high voltage having a first voltage range between the first low voltage and the first high voltage are divided into a plurality of gamma voltages of a first polarity during a first interval. A second low voltage and a second high voltage having a second voltage range between the second low voltage and the second high voltage are divided into a plurality of gamma voltages of a second polarity during a second interval.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to Korean PatentApplication No. 2007-46205, filed on May 11, 2007 in the KoreanIntellectual Property Office (KIPO), the contents of which are hereinincorporated by reference in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for generating a gammavoltage, a driving circuit for performing the method and a displaydevice having the driving circuit. More particularly, the presentinvention relates a method for generating a gamma voltage, a drivingcircuit for performing the method capable of decreasing manufacturingcosts thereof, and a display device having the driving circuit.

2. Description of the Related Art

Generally, a liquid crystal display (LCD) panel includes a gate line, asource line, a switching element, and a pixel electrode. The gate lineand the source line are formed from different metal layers. Theswitching element is electrically connected to the gate line and thesource line. The pixel electrode is formed from a transparent conductivematerial to be electrically connected to the switching element. The LCDpanel includes a common electrode facing the pixel electrode. The pixelelectrode, the common electrode and a liquid crystal layer interposedbetween the pixel electrode and the common electrode define a liquidcrystal capacitor. A storage common electrode formed from the gate metallayer and the pixel electrode define a storage capacitor.

The LCD panel includes a liquid crystal capacitor, a storage capacitorand a parasitic capacitor between a gate electrode and a sourceelectrode of the switching element. The liquid crystal capacitor, thestorage capacitor and the parasitic capacitors may define a kickbackvoltage ‘Vck’, which is defined by the following Equation 1.

$\begin{matrix}{{Vck} = {\frac{Cgs}{{Clc} + {Cst} + {Cgs}}\left( {{Von} - {Voff}} \right)}} & {{Equation}\mspace{20mu} 1}\end{matrix}$wherein ‘Vck’ represents a kickback voltage, ‘Clc’ represents the liquidcrystal capacitance of the liquid crystal capacitor, ‘Cst’ representsthe storage capacitance of the storage capacitor, ‘Cgs’ represents theparasitic capacitance between a gate electrode and a source electrode,‘Von’ represents a gate-on voltage, and ‘Voff’ represents a gate-offvoltage. The liquid crystal capacitance Clc is defined as ∈A/d, wherein‘∈’ represents the dielectric constant of the liquid crystal, ‘A’represents the size of a pixel electrode, and ‘d’ represents the cellgap of the liquid crystal layer.

Referring to Equation 1, the liquid crystal capacitance Clc has adifferent value according to the liquid crystal phase, so that thekickback voltage Vck has a different value for every gradation of liquidcrystal phase. For example, when the liquid crystal molecules are in atwisted nematic (TN) mode and a normally white mode, the kickbackvoltages of each of 64 gradations are defined by the following Equation2.Vck(0Gray)<Vck(1Gray)<, . . . ,<Vck(32Gray)<, . . .,<Vck(62Gray)<Vck(63Gray)  Equation 2

As shown in Equation 2, due to the difference of kickback voltages foreach gradation, when a gamma reference voltage is set by a uniquekickback voltage, flickering, afterimages, etc., may be generated.

SUMMARY OF THE INVENTION

The present invention provides a driving circuit for a display device aswell as a method for generating a gamma voltage capable of achieving asimple circuit design.

According to an aspect of the present invention, a method of generatinga gamma voltage comprises, generating a first voltage range lyingbetween a first low voltage and a first high voltage; dividing the firstvoltage range into a plurality of gamma voltages of a first polarityduring a first interval; generating a second voltage range differentfrom the first voltage range lying between a second low voltage and asecond high voltage; and dividing the second voltage range into aplurality of gamma voltages of a second polarity during a secondinterval.

In another example driving circuit according to the present invention,the driving circuit includes a voltage generating part and a gammavoltage generating part. The voltage generating part generates a firstlow voltage and a first high voltage having a first voltage range, whichis a voltage range between the first low voltage and the first highvoltage, and generates a second low voltage and a second high voltagehaving a second voltage range, which is a voltage range between thesecond low voltage and the second high voltage. The gamma voltagegenerating part includes a plurality of resistors serially coupled toeach other, divides the first low voltage and the first high voltage togenerate a plurality of gamma voltages of a first polarity, and dividesthe second low voltage and the second high voltage to generate aplurality of gamma voltages of a second polarity.

In another example display device according to the present invention,the display device includes a display panel, a voltage generating part,a gamma voltage generating part and a source driving part. The displaypanel includes pixel parts electrically connected to a source line and agate line crossing the source line. The voltage generating partgenerates a first low voltage and a first high voltage having a firstvoltage range, which is a voltage range between the first low voltageand the first high voltage, and generates a second low voltage and asecond high voltage having a second voltage range, which is a voltagerange between the second low voltage and the second high voltage. Thegamma voltage generating part includes a plurality of resistors seriallycoupled to each other, divides the first low voltage and the first highvoltage to generate a plurality of gamma voltages of a first polarity,and divides the second low voltage and the second high voltage togenerate a plurality of gamma voltages of a second polarity. The sourcedriving part generates a plurality of gradation voltages of the firstand second polarities by using the gamma voltages of the first andsecond polarities to output the source line.

According to the present invention, display quality may be enhanced.Furthermore, a gamma voltage generating circuit may be simplified, sothat manufacturing costs of the gamma voltage generating circuit and thedisplay device may be decreased.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other advantages of the present invention will becomereadily apparent by reference to the following detailed description whenconsidered in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic plan view illustrating a display device accordingto an exemplary embodiment of the present invention;

FIG. 2 is a block diagram illustrating the driving circuit of FIG. 1;

FIG. 3 is a graph showing a symmetric voltage-transmittance (V-T) curveand an asymmetric V-T curve.

FIG. 4 is a partial circuit diagram illustrating a first section of thevoltage generating part of FIG. 2, which generates a low voltage and ahigh voltage;

FIG. 5 is a partial circuit diagram illustrating a second section of thevoltage generating part of FIG. 2, which generates a common voltage;

FIG. 6 is a graph showing an asymmetric V-T curve obtained from thevoltage generating part of FIGS. 4 and 5;

FIG. 7 is a circuit diagram illustrating the gamma voltage generatingpart of FIG. 2; and

FIG. 8 is a partial circuit diagram illustrating the source driving partof FIG. 2.

DESCRIPTION OF THE EMBODIMENTS

Hereinafter, the present invention will be described in detail withreference to the accompanying drawings.

FIG. 1 is a schematic plan view illustrating a display device accordingto an exemplary embodiment of the present invention. FIG. 2 is a blockdiagram illustrating the driving circuit of FIG. 1.

Referring to FIGS. 1 and 2, a display device includes a display panel100 and a driving circuit 200 that drives the display panel 100.

The display panel 100 includes a display area DA displaying an image,and first and second peripheral areas PA1 and PA2 surrounding thedisplay area DA. A plurality of pixel parts electrically connected to aplurality of source lines DL1 to DLi and a plurality of gate lines GL1to GLj is formed in the display area DA. Here, ‘i’ and ‘j’ are naturalnumbers. Each of the pixel parts includes a switching element TFT, aliquid crystal capacitor CLC and a storage capacitor CST. In the presentexemplary embodiment, the display panel 100 is in a twisted nematic (TN)mode and a normally white mode.

The driving circuit 200 includes a main driving part 210, a sourcedriving part 230 and a gate driving part 250. The main driving part 210is disposed on a flexible printed circuit board (FPCB) 300 electricallyconnected to the display panel 100. The source driving part 230 isdisposed in the first peripheral area PA1 adjacent to end portions ofthe source lines DL1 to DLi, and the gate driving part 250 is disposedin the second peripheral area PA2 adjacent to end portions of the gatelines GL1 to GLj.

The main driving part 210 includes a timing control part 211, a voltagegenerating part 213 and a gamma voltage generating part 215. The timingcontrol part 211 provides the source driving part 230 with a data signalreceived from an external device. The timing control part 211 controlsthe main driving part 210, the source driving part 230 and the gatedriving part 250, based on a control signal that is received from anexternal device.

The voltage generating part 213 generates a plurality of drivingvoltages, and outputs the driving voltages in response to the control ofthe timing control part 211. For example, the driving voltages include agate-on voltage Von, a gate-off voltage Voff, a first common voltageVCOM1, a second common voltage VCOM2, a first low voltage Vb1, a firsthigh voltage Vw1, a second low voltage Vb2, and a second high voltageVw2.

The voltage generating part 213 provides the gate driving part 250 withthe gate-on and gate-off voltages Von and Voff, and provides the liquidcrystal capacitor CLC of the panel 100 with the first and second commonvoltages VCOM1 and VCOM2. The first common voltage VCOM1 has an oppositephase to the second common voltage VCOM2 with respect to a referencevoltage Vr.

The voltage generating part 213 provides the first common voltage VCOM1to the panel 100 during an N-th horizontal interval and provides thesecond common voltage VCOM2 to the panel 100 during an (N+1)-thhorizontal interval, based on the control of the timing control part211. Here, ‘N’ is a natural number. For example, the second commonvoltage VCOM2 has a first polarity with respect to the reference voltageVr, and the first common voltage VCOM1 has a second polarity withrespect to the reference voltage Vr. Hereafter, the first polarity willcorrespond to a negative polarity, and the second polarity willcorrespond to a positive polarity.

The voltage generating part 213 provides the first and second lowvoltages Vb1 and Vb2 and the first and second high voltages Vw1 and Vw2to the gamma voltage generating part 215, based on a line inversionsignal POL provided from the timing control part 211. For example, thetiming control part 211 provides the line inversion signal of ‘0’ to thevoltage generating part 213 during the N-th horizontal interval andprovides the line inversion signal of ‘1’ to the voltage generating part213 during the (N+1)-th horizontal interval.

The voltage generating part 213 provides the first low voltage Vb1 andthe first high voltage Vw1 to the gamma voltage generating part 215during the N-th horizontal interval and provides the second low voltageVb2 and the second high voltage Vw2 to the gamma voltage generating part215 during the (N+1)-th horizontal interval.

The first low voltage Vb1 and the first high voltage Vw1 have a firstvoltage range, and are smaller than the first common voltage VCOM1. Thesecond low voltage Vb2 and the second high voltage Vw2 have a secondvoltage range and are larger than the second common voltage VCOM2. Thefirst and second voltage ranges are different from each other.

The gamma voltage generating part 215 generates a plurality of negativegamma voltages by using the first low voltage Vb1 and the first highvoltage Vw1 during the N-th horizontal interval and generates aplurality of positive gamma voltages by using the second low voltage Vb2and second high voltage Vw2 during the (N+1)-th horizontal interval.

The source driving part 230 converts the data signals provided from thetiming control part 211 into gradation voltages D1 to Di by using thegamma voltages to output a plurality of source lines DL1 to DLi, basedon the control of the timing control part 211. For example, the sourcedriving part 230 outputs negative gradation voltages to the source linesduring the N-th horizontal interval when the voltage generating part 213provides the first common voltage VCOM1 to the panel 100. The sourcedriving part 230 outputs positive gradation voltages to the source linesduring the (N+1)-th horizontal interval when the voltage generating part213 provides the second common voltage VCOM2 to the display panel 100.Therefore, the display panel 100 is operated by a line inversion mode.

The gate driving part 250 generates gate signals G1 to Gj by using thegate-on/off voltages Von and Voff, based on the control of the timingcontrol part 211, and outputs the gate signals G1 to Gj to the gatelines GL1 to GLj.

Hereinafter, a method of generating the negative and positive gammavoltages having the asymmetric structure using the first and secondvoltage ranges that are different from each other will be described indetail with reference to the following FIG. 3.

FIG. 3 is a graph showing a symmetric voltage-transmittance (V-T) curveand an asymmetric V-T curve.

Referring to FIG. 3, the symmetric V-T curve is obtained when a kickbackvoltage corresponding to a halftone, for example, a kickback voltageVck(32) corresponding to a 32^(nd) gradation among 64 gradations isadopted to all gradations.

The symmetric V-T curve includes a symmetric negative V-T curve SNG anda symmetric positive V-T curve SPG that are symmetric with each otherwith respect to a reference voltage Vr.

The symmetric negative V-T curve SNG shows a transmittance with respectto the negative gamma voltages −V0s to −Vns, and the symmetric positiveV-T curve SPG shows a transmittance with respect to the positive gammavoltages +V0s to +Vns.

The negative and positive gamma voltages −V0s to −Vns and +V0s to +Vnsare generated by using a first power voltage Vb and a second powervoltage Vw having an opposite phase to the first power voltage Vb withrespect to the reference voltage Vr. For example, the first powervoltage Vb is ‘0 V’, the second power voltage Vw is ‘AVDD’, and thereference voltage Vr is an average voltage

$\frac{AVDD}{2}$of the first and second voltages Vb and Vw.

A common voltage corresponding to the negative gamma voltage is a highsignal HIGH and a common voltage corresponding to the positive gammavoltage is a low signal LOW. The high signal HIGH is generated by addinga constant voltage ‘a’ to the second power voltage Vw. The low signalLOW is generated by subtracting the constant voltage ‘a’ from the firstpower voltage Vb.

The asymmetric V-T curve is a V-T curve, in which a kickback voltageVck(white) corresponds to a white gradation and a kickback voltageVck(black) corresponding to a black gradation are adopted in thesymmetric V-T curve. The asymmetric V-T curve includes an asymmetricnegative V-T curve ANG and an asymmetric positive V-T curve APG.

A first adjustment value ‘b’ and a second adjustment value ‘w’ arecalculated using the kickback voltage Vck(white) corresponding to awhite gradation and the kickback voltage Vck(black) corresponding to ablack gradation. A first shift value ‘B’ and a second shift value ‘W’are calculated using the first and second adjustment values ‘b’ and ‘w’.Here, the first and second movements ‘B’ and ‘W’ are proportional to thefirst and second adjustment values ‘b’ and ‘w’.

The first and second shift values ‘B’ and ‘W’, and the first and secondadjustment values ‘b’ and ‘w’ are defined by the following Equation 3.w=Vck(white)−Vck(middle)b=Vck(middle)−Vck(black)w∝W,b∝B  Equation 3

The asymmetric negative V-T curve ANG is a line segment that connects atransmittance corresponding to a low gradation gamma voltage +V0a with atransmittance corresponding to a high gradation gamma voltage +Vns. Thetransmittance corresponding to a low gradation gamma voltage +V0a isobtained by shifting a low gradation gamma voltage −V0s of the symmetricnegative V-T curve SNG by the first adjustment value ‘b’. Thetransmittance corresponding to high gradation gamma voltage +Vns isobtained by shifting the high gradation gamma voltage +Vns of thesymmetric negative V-T curve SNG by the second adjustment value ‘w’.

The asymmetric negative V-T curve ANG shows a transmittance with respectto the negative gamma voltages −V0a to −Vna. The negative gamma voltages−V0a to −Vna are generated by using the first low voltage Vb1 and thefirst high voltage Vw1 having the first voltage range.

In this case, the first low voltage Vb1 is a voltage ‘0-B’ that is movedtoward the left by as much as the first shift value ‘B’ from the firstpower voltage ‘Vb=0 V’. The first high voltage Vw1 is a voltage ‘AVDD+B’that is moved toward the right by as much as the second shift value ‘W’from the second power voltage ‘Vw=AVDD’.

The asymmetric positive V-T curve APG is a line segment that connects atransmittance corresponding to a low gradation gamma voltage −V0a with atransmittance corresponding to a transmittance corresponding to a highgradation gamma voltage −Vna. The transmittance corresponding to the lowgradation −V0a is obtained by shifting the transmittance correspondingto a low gradation gamma voltage −Vs of the symmetric positive V-T curveSPG by the first adjustment value ‘b’. The transmittance correspondingto the high gradation −Vna is obtained by shifting the transmittancecorresponding to a high gradation gamma voltage −Vns of the symmetricpositive V-T curve SPG by the second adjustment value ‘w’.

The asymmetric positive V-T curve APG shows a transmittance with respectto the positive gamma voltages +V0a to +Vna. The positive gamma voltages+V0a to +Vna are generated by using the second low voltage Vb2 and thesecond high voltage Vw2 having the second voltage range.

In this case, the second low voltage Vb2 is a voltage ‘AVDD−B’ that isobtained by leftward shifting the second power voltage ‘Vw=AVDD’ by thefirst shift value ‘B’. The second high voltage Vw2 is a voltage ‘0+W’that is obtained by rightward shifting the first power voltage ‘Vb=0 V’by the second shift value ‘W’.

The asymmetric gamma V-T curves ANG and APG are summarized in thefollowing Table 1.

TABLE 1 Range of Polarity Vb Vw Gamma Voltage VCOM Negative 0 − B AVDD +W (0 − B) to High (AVDD + W) Positive AVDD − B 0 + W (AVDD − B) to (W)Low

Referring to Table 1, the asymmetric negative gamma voltages aregenerated to be in the first voltage range of ‘0-B’ to ‘AVDD+W’, and theasymmetric positive gamma voltages are generated to be in the secondvoltage range of ‘AVDD−B’ to ‘W’.

FIG. 4 is a partial circuit diagram illustrating a first section of thevoltage generating part of FIG. 2, which generates a low voltage and ahigh voltage.

Referring to FIGS. 2 and 4, the voltage generating part 213 includes anAND gate 201 and a first operational amplifier (op-amp) 203.

The AND gate 201 includes a first input terminal 201 a, a second inputterminal 201 b and an output terminal 201 c. The first input terminal201 a receives a line inversion signal POL provided from the timingcontroller 211 and the second input terminal 201 b receives a powervoltage AVDD. The first input terminal 201 a receives ‘0’ or ‘1’ and thesecond input terminal 201 b receives the power voltage AVDD of a DCsignal, that is, ‘1’.

Therefore, the AND gate 201 outputs a first low voltage Vb1 of ‘0’ or asecond low voltage Vb2 of ‘1’ through the output terminal 201 c inresponse to the line inversion signal POL ‘0’ or ‘1’. Hereinafter, thefirst low voltage will be described as ‘0’ and the second low voltagewill be described as ‘1’.

The output terminal 201 c is connected to a first output part 213 a ofthe voltage generating part 213. The first low voltage Vb1 or the secondlow voltage Vb2 is outputted through the first output part 213 a.

A first resistor R1 and a second resistor R2 are serially connected toeach other between the second input terminal 201 b and a ground terminalGND. The ground terminal has a voltage of 0 V.

A voltage of the second resistor R2 is provided to a reference terminal203 a of the first op-amp 203 to be a first reference signal of thefirst op-amp 203. A level of the first reference signal is defined bythe second resistor R2. The level of the first reference signal isdefined to be larger than an average voltage

$\frac{AVDD}{2}$of the first and second low voltages Vb1 and Vb2.

The level of the first reference signal is

$\frac{AVDD}{2} + {\frac{\left( {W + B} \right)}{2}.}$Here, ‘W’ and ‘B’ are the first shift value B and the second shift valueW with the respect to the kickback voltage of the white gradation andthe kickback voltage of the black gradation, as shown in FIG. 3.

The second resistor R2 may be a fixed resistor or a variable resistor.The level of the first reference signal may be adjusted by using thevariable resistor in a process of flicker tuning.

The op-amp 203 includes the reference terminal 203 a receiving thereference signal, an input terminal 203 b receiving an output signal ofthe AND gate 201, and an output terminal 203 c outputting an outputsignal of the op-amp 203. The output terminal 203 c of the op-amp 203 isconnected to a second output part 213 b of the voltage generating part213 to output a first high voltage Vw1 or a second high voltage Vw2.

A third resistor R3 connects the output terminal 201 c of the AND gate201 to the input terminal 203 b of the first op-amp 203. Another thirdresistor R3 connects the input terminal 203 b of the first op-amp 203 tothe output terminal 203 c of the first op-amp 203. The first op-amp 203amplifies the first low voltage Vb1 or the second low voltage Vb2outputted from the AND gate 201 to output the first high voltage Vw1 orthe second high voltage Vw2.

Hereinafter, a process, in which the first and second low voltages Vb1and Vb2, and the first and second high voltages Vw1 and Vw2 aregenerated by the voltage generating part 213, will be described.

A negative mode, in which the voltage generating part 213 receives theline inversion signal POL of ‘0’, will be described.

The AND gate 201 outputs ‘0 V’ in response to the line inversion signalPOL of ‘0’. Thus, a voltage of a node N becomes ‘0 V’ and the firstoutput part 213 a of the voltage generating part 213, which is connectedto the node N, outputs ‘0 V’ that is the first low voltage Vb1.

The reference terminal 203 a of the first op-amp 203 receives the firstreference signal

$\frac{AVDD}{2} + \frac{\left( {W + B} \right)}{2}$defined by the second resistor R2. The input terminal 203 b of the firstop-amp 203 receives an input voltage

$\frac{AVDD}{2} + \frac{\left( {W + B} \right)}{2}$equal to the first reference signal in accordance with characteristicsof the first op-amp 203.

The voltage of the node N is ‘0 V’ and the input voltage of the inputterminal 203 b is

${‘{\frac{AVDD}{2} + \frac{\left( {W + B} \right)}{2}}’},$so that a first current I1 between the node N and the second output part213 b is defined by the following Equation 4.

$\begin{matrix}{\begin{matrix}{{I\; 1} = \frac{{V(N)} - \frac{{A\; V\; D\; D} + \left( {W + B} \right)}{2}}{R\; 3}} \\{= \frac{0 - \frac{{A\; V\; D\; D} + \left( {W + B} \right)}{2}}{R\; 3}} \\{= \frac{\frac{{A\; V\; D\; D} + \left( {W + B} \right)}{2}}{R\; 3}}\end{matrix}\left( {{Here},{{V(N)} = 0}} \right)} & {{Equation}\mspace{20mu} 4}\end{matrix}$

According to the first current I1, the first high voltage Vw1 outputtedfrom the second output part 213 b is defined by a difference between theinput voltage of the input terminal 203 b and a voltage of the thirdresistor R3, as in the following Equation 5.

$\begin{matrix}\begin{matrix}{{{Vw}\; 1} = {\frac{{AVDD} + \left( {W + B} \right)}{2} - {{Vf}\; 1}}} \\{= {\frac{{AVDD} + \left( {W + B} \right)}{2} - {R\;{3 \cdot I}\; 1}}} \\{= {\frac{{AVDD} + \left( {W + B} \right)}{2} + {R\;{3 \cdot \frac{\frac{{AVDD} + \left( {W + B} \right)}{2}}{R\; 3}}}}} \\{= {{AVDD} + \left( {W + B} \right)}}\end{matrix} & {{Equation}\mspace{20mu} 5}\end{matrix}$

For a negative mode, the first output part 213 a of the voltagegenerating part 213 outputs the first low voltage Vb1 of ‘0 V’, and thesecond output part 213 b of the voltage generating part 213 outputs thefirst high voltage Vw1 of ‘AVDD+(W+B)’. That is, the first high voltageVw1 is obtained by adding a voltage (W+B) to the second low voltage(Vb2=AVDD).

A positive mode, in which the voltage generating part 213 receives theline inversion signal POL of ‘1’, will be described.

The AND gate 201 outputs ‘AVDD’ in response to the line inversion signalPOL of ‘1’. Thus, a voltage of a node N is ‘AVDD’ and the first outputpart 213 a of the voltage generating part 213 connected to the node Noutputs ‘AVDD’ that is the second low voltage Vb2.

The reference terminal 203 a of the first op-amp 203 receives the firstreference signal

$\frac{AVDD}{2} + \frac{\left( {W + B} \right)}{2}$defined by the second resistor R2. The input terminal 203 b of the firstop-amp 203 receives an input voltage

$\frac{AVDD}{2} + \frac{\left( {W + B} \right)}{2}$equal to the first reference signal in accordance with characteristicsof the first op-amp 203.

The voltage of the node N is ‘AVDD’ and the input voltage of the inputterminal 203 b is

${{\backprime\frac{AVDD}{2}} + {\frac{\left( {W + B} \right)}{2}\prime}},$so that a first current I1 between the node N and the second output part213 b is defined by the following Equation 6.

$\begin{matrix}{\begin{matrix}{{I\; 1} = \frac{{V(N)} - \frac{{AVDD} + \left( {W + B} \right)}{2}}{R\; 3}} \\{= \frac{{AVDD} - \frac{{AVDD} + \left( {W + B} \right)}{2}}{R\; 3}}\end{matrix}\left( {{Here},{{V(N)} = {AVDD}}} \right)} & {{Equation}\mspace{20mu} 6}\end{matrix}$

According to the first current I1, the second high voltage Vw2 outputfrom the second output part 213 b is defined by the difference betweenthe input voltage of the input terminal 203 b and the voltage of thethird resistor R3, as in the following Equation 7.

$\begin{matrix}\begin{matrix}{{{Vw}\; 2} = {\frac{{AVDD} + \left( {W + B} \right)}{2} - {{Vf}\; 1}}} \\{= {\frac{{AVDD} + \left( {W + B} \right)}{2} - {R\;{3 \cdot I}\; 1}}} \\{= {\frac{{AVDD} + \left( {W + B} \right)}{2} - {R\;{3 \cdot}}}} \\{\frac{{AVDD} - \frac{{AVDD} + \left( {W + B} \right)}{2}}{R\; 3}} \\{= {\frac{{AVDD} + \left( {W + B} \right)}{2} - {AVDD} + \frac{{AVDD} + \left( {W + B} \right)}{2}}} \\{= {W + B}}\end{matrix} & {{Equation}\mspace{20mu} 7}\end{matrix}$

For the positive mode, the first output part 213 a of the voltagegenerating part 213 outputs the second low voltage Vb2, ‘AVDD’, and thesecond output part 213 b of the voltage generating part 213 outputs thesecond high voltage Vw2, ‘W+B’. That is, the second high voltage Vw2 isa voltage added the first low voltage (Vb2=0 V) to (W+B).

FIG. 5 is a partial circuit diagram illustrating a second section of thevoltage generating part of FIG. 2, which generates a common voltage.

Referring to FIGS. 2 and 5, the voltage generating part 213 includes aninput part 204 that receives a high signal HIGH and a low signal LOWhaving an opposite phase to the high signal HIGH with respect to areference voltage Vr, and a second op-amp 205 amplifying and outputtingthe high and low signals HIGH and LOW. The high signal HIGH is obtainedby adding a constant voltage ‘a’ to the second low voltage Vb2, and thelow signal LOW is obtained by subtracting the constant voltage ‘a’ fromthe first low voltage Vb1.

The second op-amp 205 includes a reference terminal 205 a, an inputterminal 205 b, and an output terminal 205 c connected to a third outputpart 213 c of the voltage generating part 213. The reference terminal205 a receives a second reference signal

$\frac{{HIGH} + {LOW} + B}{2}.$A circuit generating the second reference signal includes a plurality offifth resistors R5 generating an average voltage

$\frac{{HIGH} + {LOW}}{2}$of the high and low voltages HIGH and LOW received by two terminals ofthe circuit, and a sixth resistor R6 connects the fifth resistors R5 toR5 in order to adjust the average voltage

$\frac{{HIGH} + {LOW}}{2}$to be the second reference signal

$\frac{{HIGH} + {LOW} + B}{2}.$

The sixth resistor R6 may be a fixed resistor or a variable resistor. Alevel of the first common voltage VCOM1 and a level of the second commonvoltage VCOM2 may be adjusted by using the variable resistor in aprocess of flicker tuning.

The input terminal 205 b of the second op-amp 205 receives an inputvoltage equal to the second reference signal

$\frac{{HIGH} + {LOW} + B}{2}$in accordance with op-amp characteristics.

A seventh resistor R7 connects the input part 204 to the input terminal205 b of the second op-amp 205, and another seventh resistor R7 connectsthe input terminal 205 b to the output terminal 205 c of the secondop-amp 205.

When the input part 204 receives the low signal LOW, a second current I2flowing between the input part 204 and the third output part 213 c isdefined by the following Equation 8.

$\begin{matrix}{{I\; 2} = \frac{{LOW} - \frac{{HIGH} + {LOW} + B}{2}}{R\; 7}} & {{Equation}\mspace{20mu} 8}\end{matrix}$

The first common voltage VCOM1 output from the third output part 213 cis defined by a voltage difference between the input terminal 205 b ofthe second op-amp 205 and a voltage Vf2 of the seventh resistor R7, asin the following Equation 9.

$\begin{matrix}\begin{matrix}{{{VCOM}\; 1} = {\frac{{HIGH} + {LOW} + B}{2} - {{Vf}\; 2}}} \\{= {\frac{{HIGH} + {LOW} + B}{2} - {R\;{7 \cdot {Vf}}\; 2}}} \\{= {\frac{{HIGH} + {LOW} + B}{2} - {R\;{7 \cdot}}}} \\{\frac{\left( {{LOW} - \frac{{HIGH} + {LOW} + B}{2}} \right)}{R\; 7}} \\{= {{HIGH} + B}}\end{matrix} & {{Equation}\mspace{20mu} 9}\end{matrix}$

When the input part 204 receives the high signal HIGH, a second currentI2 between the input part 204 and the third output part 213 c is definedby the following Equation 10.

$\begin{matrix}{{I\; 2} = \frac{\left( {{HIGH} - \frac{{HIGH} + {LOW} + B}{2}} \right)}{R\; 7}} & {{Equation}\mspace{20mu} 10}\end{matrix}$

The second common voltage VCOM2 outputted from the third output part 213c is defined by a voltage difference between the input terminal 205 b ofthe second op-amp 205 and a voltage Vf2 of the seventh resistor R7, asin the following Equation 11.

$\begin{matrix}\begin{matrix}{{{VCOM}\; 2} = {\frac{{HIGH} + {LOW} + B}{2} - {{Vf}\; 2}}} \\{= {\frac{{HIGH} + {LOW} + B}{2} - {R\;{7 \cdot I}\; 2}}} \\{= {\frac{{HIGH} + {LOW} + B}{2} - {R\;{7 \cdot}}}} \\{\frac{\left( {{HIGH} - \frac{{HIGH} + {LOW} + B}{2}} \right)}{R\; 7}} \\{= {{LOW} + B}}\end{matrix} & {{Equation}\mspace{20mu} 11}\end{matrix}$

Thus, the driving of the voltage generating part 213 is summarized inthe following Table 2.

TABLE 2 POL Vb Vw Range of the voltage VCOM Polarity 0 0 AVDD + (W + B)‘0’ to ‘AVDD + (W + B)’ High + B Negative 1 AVDD (W + B) ‘AVDD’ to ‘(W +B)’ Low + B Positive

FIG. 6 is a graph showing an asymmetric V-T curve obtained from thevoltage generating part of FIGS. 4 and 5.

Referring to FIGS. 3 and 6, in the case of the negative mode, thevoltage generating part 213 generates the first low voltage Vb1 of 0 V,the first high voltage Vw1 of ‘AVDD+(W+B)’ and the first common voltageVCOM1 of ‘HIGH+B’. A range of the asymmetric negative gamma voltages is‘0’ to ‘AVDD+(W+B).

The range of the asymmetric negative gamma voltages in a range of ‘0 toAVDD+(W+B)’ is obtained by rightward shifting ‘0-B to AVDD+W’ in FIG. 3by the first shift value B. The first common voltage VCOM1 is obtainedby rightward shifting the high signal HIGH shown in FIG. 3 by the firstshift value B.

In the case of the positive mode, the voltage generating part 213generates the second low voltage Vb2 of AVDD, the second high voltageVw2 of ‘(W+B)’ and the second common voltage VCOM2 of ‘LOW+B’. A rangeof the asymmetric positive gamma voltages is ‘AVDD’ to ‘(W+B)’.

The range of the asymmetric positive gamma voltages in a range of ‘AVDDto (W+B)’ is obtained by rightward shifting the asymmetric positivegamma voltages in a range of ‘AVDD-B’ to ‘W’ in FIG. 3 by the firstshift value B. The second common voltage VCOM2 is obtained by rightwardshifting the low signal LOW shown in FIG. 3 by the first shift value B.

Therefore, the voltage generating part 213 sets the first and secondvoltages Vb1 and Vb2, and amplifies the first and second voltages Vb1and Vb2 to the first and second high voltages Vw1 and Vw2 through thefirst op-amp 203. The voltage generating part 213 generates the firstlow voltage Vb1 and the first high voltage Vw1 in the negative mode, andgenerates the second low voltage Vb2 and the second high voltage Vw2 inthe positive mode, respectively. The voltage generating part 213generates the low and high voltages different from each other in thenegative and positive modes, so that the voltage generating part 213 maybe simplified.

FIG. 7 is a circuit diagram illustrating the gamma voltage generatingpart of FIG. 2. FIG. 8 is a partial circuit diagram illustrating thesource driving part of FIG. 2.

Referring to FIG. 7, a gamma voltage generating part 215 includes afirst power terminal 215 a, a second power terminal 215 b and a resistorstring part 215 c.

The first power terminal 215 a receives the first and second lowvoltages Vb1 and Vb2. The first power terminal 215 a receives the firstlow voltage Vb1 in the horizontal interval of N-th, and receives thesecond low voltage Vb2 in the horizontal interval of (N+1)-th.

The second power terminal 215 b receives the first and second highvoltages Vw1 and Vw2. The second power terminal 215 b receives the firsthigh voltage Vw1 in the horizontal interval of N-th, and receives thesecond high voltage Vw2 in the horizontal interval of (N+1)-th.

The resistor string part 215 c includes a plurality of resistors R0 toRn+1 that are serially coupled to each other. A plurality of outputterminals is formed between the resistors R0 to Rn+1. The resistorstring part 215 c divides the low and high voltages that are applied tothe first and second power terminals 215 a and 215 b into a plurality ofgamma voltages.

For example, the resistor string part 215 c divides the first lowvoltage Vb1 and the first high voltage Vw1 that are applied to the firstand second power terminals 215 a and 215 b into a plurality of thenegative gamma voltages, −V0, −V1, . . . , −Vn−1 and −Vn. The resistorstring part 215 c divides the second low voltage Vb2 and the second highvoltage Vw2 that are applied to the first and second power terminals 215a and 215 b into a plurality of the positive gamma voltages, +V0, +V1, .. . , +Vn−1 and +Vn.

The plurality of negative gamma voltages and the plurality of positivegamma voltages ±V0, ±V1, . . . , ±Vn−1 and ±Vn are provided with thesource driving part 230. The source driving part 230 includes agradation voltage generating part 230 a.

Referring to FIG. 8, the gradation voltage generating part 230 aincludes a resistor string having a plurality of resistors R1 to Rk thatare electrically connected in series. Each of the gamma voltages ±V0,±V1, . . . , ±Vn−1 and ±Vn are applied to the resistors R1, . . . , Rk,respectively, so that a plurality of gradation voltages, for example, 64gradation voltages ±g0, ±g1, . . . , ±g62 and ±g63 corresponding to thetotal gradation is generated.

For example, each of the negative gamma voltages −V0, −V1, . . . , −Vn−1and −Vn are applied to the resistors R1, . . . , Rk, respectively, sothat a plurality of negative gradation voltages, −g0, −g1, . . . , −g62and −g63 in the horizontal interval of N-th is outputted. Each of thepositive gamma voltages +V0, +V1, . . . , +Vn−1 and +Vn are applied tothe resistors R1, . . . , Rk, respectively, so that a plurality ofpositive gradation voltages, +g0, +g1, . . . , +g62 and +g63 in thehorizontal interval of (N+1)-th is outputted.

As described above, according to the present invention, first and secondpolarity gamma voltages may be alternately generated using a gammavoltage generating circuit having one resistor string. Two terminals ofthe resistor string receive a first low voltage and a first high voltagehaving a first voltage range in a first polarity mode and receive asecond low voltage and a second high voltage having a second voltagerange in a second polarity mode to generate the first and secondpolarity gamma voltages.

Therefore, a circuit for generating the gamma voltages may be simplifiedand manufacturing costs may be decreased. Furthermore, as an asymmetricV-T curve is adapted to the gamma voltage generating circuit, displayquality problems, such as flickering, afterimages, etc. may be improved.

Although the exemplary embodiments of the present invention have beendescribed, it is understood that the present invention should not belimited to these exemplary embodiments but various changes andmodifications can be made by one ordinary skilled in the art within thespirit and scope of the present invention as hereinafter claimed.

What is claimed is:
 1. A method for generating kickback-compensatinggamma voltages when in respective positive and negative polarity modesof a Liquid Crystal Display (LCD) system that exhibits a variablekickback effect for each respective pixel transistor used to drive arespective liquid crystal pixel, where the kickback effect is dependenton the drive polarity mode then in effect and on a grayscale gradationto be presented by the respective liquid crystal pixel, the methodcomprising: establishing a first low voltage (Vb1) and a first highvoltage (Vw1) for use in generating respective, negative polarity gammavoltages when the negative polarity mode is true; using the establishedfirst low voltage (Vb1) and first high voltage (Vw1) when the negativepolarity mode is true to generate the respective negative polarity gammavoltages, wherein magnitudes of the generated negative polarity gammavoltages are at least partially determined according to the establishedfirst low and high voltages (Vb1, Vw1) to thereby compensate in thenegative polarity mode for corresponding kickback effects; establishinga second low voltage (Vb2) and a second high voltage (Vw2) for use ingenerating respective positive polarity gamma voltages when the positivepolarity mode is true, where Vb2 is different from Vb1 and where Vw2 isdifferent from Vw1; and using the established second low voltage (Vb2)and second high voltage (Vw2) when the positive polarity mode is true togenerate the respective positive polarity gamma voltages, whereinmagnitudes of the generated positive polarity gamma voltages are atleast partially determined according to the established second low andhigh voltages (Vb2, Vw2) to thereby compensate in the positive polaritymode for corresponding kickback effects.
 2. The method of claim 1,wherein a first of the positive and negative polarity modes occurs in arespective first gate line activating interval which is an N-th (N is anatural number) horizontal interval of the LCD system and the other ofthe positive and negative polarity modes occurs in a respective secondinterval which is an (N+1)-th horizontal interval.
 3. A driving circuitfor use in generating kickback-compensating gamma voltages forrespective positive and negative polarity modes of a Liquid CrystalDisplay (LCD) system that exhibits a variable kickback effect for eachrespective pixel transistor used to drive a respective liquid crystalpixel, where the kickback effect is dependent on the drive polarity modethen in effect and on a grayscale gradation to be presented by therespective liquid crystal pixel, the driving circuit comprising: avoltage generating part configured to output a first low voltage (Vb1)and a first high voltage (Vw1) for use in generating respective,negative polarity gamma voltages for said LCD system when the negativepolarity mode is true in said LCD system and to output a second lowvoltage (Vb2) and a second high voltage (Vw2) for use in generatingrespective positive polarity gamma voltages for said LCD system when thepositive polarity mode is true, where Vb2 is different from Vb1 andwhere Vw2 is different from Vw1; and a gamma voltages generating part,operatively coupled to the voltage generating part to receive therefromeither the first low and high voltages (Vb1, Vw1) or the second low andhigh voltages (Vb2, Vw2) as control signals, the gamma voltagesgenerating part including a plurality of resistors serially coupled toeach other, the gamma voltages generating part being configured togenerate the respective, negative polarity gamma voltages in a rangeextending from the first low voltage to the first high voltage when thenegative polarity mode is true, and configured to generate therespective positive polarity gamma voltages in a range extending fromthe second low voltage to the second high voltage when the positivepolarity mode is true, wherein magnitudes of the generated gammavoltages are at least partially determined to compensate for saidvariable kickback effect of the LCD system.
 4. The driving circuit ofclaim 3, wherein the voltage generating part is configured to generate afirst common voltage and a second common voltage having an oppositephase to the first common voltage with respect to a reference voltage.5. The driving circuit of claim 4, wherein the first common voltage ishigher than the first low voltage and the first high voltage, and thesecond common voltage is lower than the second low voltage and thesecond high voltage.
 6. The driving circuit of claim 5, wherein thevoltage generating part includes: an AND gate configured to output thefirst low voltage or the second low voltage in response to a lineinversion signal; and an operational amplifier (op-amp) configured toamplify and output the first low voltage or the second low voltage tothe first high voltage or the second high voltage according to areference signal.
 7. The driving circuit of claim 6, wherein the op-ampis connected to a variable resistor to adjust the reference signal. 8.The driving circuit of claim 6, wherein the reference signal is higherthan an average voltage of the first and second low voltages.
 9. Thedriving circuit of claim 8, wherein the reference signal is defined bythe following Equation:$\frac{{{Vb}\; 1} + {{Vb}\; 2}}{2} + \frac{\left( {W + B} \right)}{2}$w ∝ W, b ∝ B w = Vck(white) − Vck(middle) b = Vck(middle) − Vck(black)wherein Vb1 is the first low voltage, Vb2 is the second low voltage,Vck(white) is a kickback voltage of a white gradation, Vck(black) is akickback voltage of a black gradation, and Vck(middle) is a kickbackvoltage of a halftone that is between the white gradation and the blackgradation.
 10. The driving circuit of claim 9, wherein the first lowvoltage Vb1, the second low voltage Vb2, the first high voltage Vw1 andthe second high voltage Vw2 are defined by the following Equation:Vw1=Vb2+(W+B)Vw2=Vb1+(W+B).
 11. The driving circuit of claim 10, wherein the firstcommon voltage VCOM1 and the second common voltage VCOM2 are defined bythe following Equation:VCOM1=(Vb2+a)+BVCOM2=(Vb1−a)+B wherein ‘a’ is a constant voltage.
 12. A liquid crystaldisplay device (LCD) that exhibits a variable kickback effect for eachrespective pixel transistor used therein to drive a respective liquidcrystal pixel, where the kickback effect is dependent on the drivepolarity mode then in effect and on a grayscale gradation to bepresented by the respective liquid crystal pixel, the LCD comprising: adisplay panel including pixel parts each electrically connected to arespective source line and to a respective gate line and each includingat least one said respective pixel transistor; a voltage generating partconfigured to output a first low voltage (Vb1) and a first high voltage(Vw1) for use in generating respective, negative polarity gamma voltagesfor said LCD system when the negative polarity mode is true in said LCDsystem and to output a second low voltage (Vb2) and a second highvoltage (Vw2) for use in generating respective positive polarity gammavoltages for said LCD system when the positive polarity mode is true,where Vb2 is different from Vb1 and where Vw2 is different from Vw1; anda gamma voltages generating part, operatively coupled to the voltagegenerating part to receive therefrom either the first low and highvoltages (Vb1, Vw1) or the second low and high voltages (Vb2, Vw2) ascontrol signals, the gamma voltages generating part including aplurality of resistors serially coupled to each other, the gammavoltages generating part being configured to generate the respective,negative polarity gamma voltages in a range extending from the first lowvoltage to the first high voltage when the negative polarity mode istrue, and configured to generate the respective positive polarity gammavoltages in a range extending from the second low voltage to the secondhigh voltage when the positive polarity mode is true, wherein magnitudesof the generated gamma voltages are at least partially determined tocompensate for said variable kickback effect of the LCD system; and asource driving part operatively coupled to the respective source linesand to the gamma voltages generating part, and configured to generate aplurality of respective source line driving voltages of the positive andnegative polarities by using the gamma voltages generated by the gammavoltages generating part.
 13. The display device of claim 12, whereinthe voltage generating part configured to generate a first commonvoltage and a second common voltage having an opposite phase to thefirst common voltage with respect to a reference voltage.
 14. Thedisplay device of claim 13, wherein the voltage generating partconfigured to output the first common voltage to the display panelduring output of the gray voltage of the first polarity to the sourceline, and is configured to output the second common voltage to the panelduring output of the gray voltage of the second polarity to the sourceline.
 15. The display device of claim 14, wherein the first commonvoltage is higher than the first low voltage and the first high voltage,and the second common voltage is lower than the second low voltage andthe second high voltage.
 16. The display device of claim 14, wherein thevoltage generating part including: an AND gate configured to output thefirst low voltage or the second low voltage in response to a lineinversion signal; and an op-amp configured to amplify and output thefirst low voltage or the second low voltage to the first high voltage orthe second high voltage according to a reference signal.
 17. The displaydevice of claim 16, wherein the reference signal is higher than anaverage voltage of the first and second low voltages.
 18. The drivingcircuit of claim 17, wherein the reference signal is defined by thefollowing Equation:$\frac{{{Vb}\; 1} + {{Vb}\; 2}}{2} + \frac{\left( {W + B} \right)}{2}$w ∝ W, b ∝ B w = Vck(white) − Vck(middle) b = Vck(middle) − Vck(black)wherein Vb1 is the first low voltage, Vb2 is the second low voltage,Vck(white) is a kickback voltage of a white gradation, Vck(black) is akickback voltage of a black gradation, and Vck(middle) is a kickbackvoltage of a halftone that is between the white gradation and the blackgradation.
 19. The driving circuit of claim 18, wherein the first lowvoltage Vb1, the second low voltage Vb2, the first high voltage Vw1 andthe second high voltage Vw2 are defined by the following Equation:Vw1=Vb2+(W+B)Vw2=Vb1+(W+B).
 20. The driving circuit of claim 19, wherein the firstcommon voltage VCOM1 and the second common voltage are defined by thefollowing Equation:VCOM1=(Vb2+a)+BVCOM2=(Vb1−a)+B wherein ‘a’ is a constant voltage.